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MC74VHC00 Quad 2-Input NAND Gate
The MC74VHC00 is an advanced high speed CMOS 2-input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V systems.
Features
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14 SO-14 D SUFFIX CASE 751A VHC00G AWLYWW 1
* * * * * * * * * * * *
High Speed: tPD = 3.7 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 32 FETs or 8 Equivalent Gates Pb-Free Packages are Available
VCC 14 B4 13 A4 12 Y4 11 B3 10 A3 9 Y3 8
14 VHC 00 ALYW G G 1
TSSOP-14 DT SUFFIX CASE 948G
14
EIAJ SO-14 M SUFFIX CASE 965 1 A L, WL Y W, WW G, G
74VHC00 ALYWG
1 A1
2 B1
3 Y1
4 A2
5 B2
6 Y2
7 GND
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Device
Figure 1. Pinout: 14-Lead Packages (Top View) FUNCTION TABLE
Inputs A L L H H B L H L H Output Y H H H L
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
1
January, 2006 - Rev. 5
Publication Order Number: MC74VHC00/D
MC74VHC00
A1 B1 A2 B2 A3 B3 A4 B4 1 2 4 5 9 10 12 13 3 Y1
6
Y2 Y = AB
8
Y3
11
Y4
Figure 2. Logic Diagram
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG VESD Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 125C (Note 4) SOIC Package TSSOP SOIC Package TSSOP Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +0.5 -20 $20 $25 $75 200 180 -65 to +150 >2000 >200 N/A $300 143 164 Unit V V V mA mA mA mA mW C V
ILATCH-UP qJA
Latch-Up Performance
mA C/W
Thermal Resistance, Junction to Ambient
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22-A114-A 2. Tested to EIA/JESD22-A115-A 3. Tested to JESD22-C101-A 4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range, All Package Types Input Rise or Fall Time VCC = 3.3 V + 0.3 V VCC = 5.0 V + 0.5 V Characteristics Min 2.0 0 0 -55 0 0 Max 5.5 5.5 VCC 125 100 20 Unit V V V C ns/V
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5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
I I IIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I II IIIIIIIII IIII I I I I IIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I IIII I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I II I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II III I I I III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIII II II II I I IIIIIIIII IIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I I I I I IIIIII II IIIIII II II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIII II IIIIII II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II IIIIII II I I I I IIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II II I I III II I II IIIIIIIIIIIIIIIIIIIIIII IIIIII II IIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II III II I I I IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIII I I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II IIIIIIIIIIIIIIIIIIIIII II II II II I I I IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII I IIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) DC ELECTRICAL CHARACTERISTICS
Symbol Symbol tPLH, tPHL VOH VOL VIH ICC Cin VIL Iin Input Capacitance Propagation Delay, A or B to Y Quiescent Supply Current Input Leakage Current Low-Level Output Voltage High-Level Output Voltage Low-Level Input Voltage High-Level Input Voltage Parameter Parameter VCC = 5.0 0.5 V VCC = 3.3 0.3 V Vin = VCC or GND Vin = 5.5 V or GND Vin = VIH or VIL IOL = 4 mA IOL = 8 mA Vin = VIH or VIL IOL = 50 mA Vin = VIH or VIL IOH = - 4 mA IOH = - 8 mA Vin = VIH or VIL IOH = - 50 mA Test Conditions Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 0 to 5.5
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V, Measured in SOIC Package)
Symbol
CPD
VOLP
VOLV
VIHD
VILD
Power Dissipation Capacitance (Note 5)
Maximum Low Level Dynamic Input Voltage
Minimum High Level Dynamic Input Voltage
Quiet Output Minimum Dynamic VOL
Quiet Output Maximum Dynamic VOL
Characteristic
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MC74VHC00
2.0 3.0 to 5.5
2.0 3.0 to 5.5
VCC V
5.5
3.0 4.5
2.0 3.0 4.5
3.0 4.5
2.0 3.0 4.5
3 1.50 VCC x 0.7 2.58 3.94 Min 1.9 2.9 4.4 Min TA = 25C TA = 25C Typ Typ 4.0 3.7 5.2 5.5 8.0 0.0 0.0 0.0 2.0 3.0 4.5 0.50 VCC x 0.3 $0.1 Max 0.36 0.36 Max 7.9 11.4 5.5 7.5 2.0 0.1 0.1 0.1 10 Typical @ 25C, VCC = 5.0 V 1.50 VCC x 0.7 2.48 3.80 Min Min TA = -40 to 85C TA = -40 to 85C 1.0 1.0 1.0 1.0 1.9 2.9 4.4 0.50 VCC x 0.3 - 0.3 $1.0 9.5 13.0 Max 0.44 0.44 Max Typ 0.3 6.5 8.5 0.1 0.1 0.1 10 20 19 TA = 25C 1.50 VCC x 0.7 2.40 3.70 Min Min TA = -55 to +125C TA = -55 to +125C 1.0 1.0 1.0 1.0 1.9 2.9 4.4 - 0.8 Max 1.5 3.5 0.8 0.50 VCC x 0.3 $2.0 Max 0.55 0.55 Max 10 14.5 7.0 9.5 0.1 0.1 0.1 10 40 Unit Unit Unit pF V V V V mA mA pF ns V V V V
MC74VHC00
TEST POINT A or B 50% tPLH Y 50% VCC *Includes all probe and jig capacitance tPHL VCC GND DEVICE UNDER TEST OUTPUT C L*
Figure 3. Switching Waveforms
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
ORDERING INFORMATION
Device MC74VHC00DR2 MC74VHC00DR2G MC74VHC00DT MC74VHC00DTG MC74VHC00DTR2 MC74VHC00DTR2G MC74VHC00MEL MC74VHC00MELG Package SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* (Pb-Free) TSSOP-14* TSSOP-14* (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) Shipping 2500 / Tape & Reel 2500 / Tape & Reel 96 Units / Rail 96 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 2000 / Tape & Reel 2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74VHC00
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE A
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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EEE CCC EEE CCC
A -V-
DIM A B C D F G H J J1 K K1 L M
MC74VHC00
PACKAGE DIMENSIONS
SO-14 M SUFFIX CASE 965-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74VHC00/D

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